Tinker Board Forum - Any way to disable 4k or force 1920x1080@60 for boot shell? TinkerOS 2.04?

My setup includes my Tinker Board => Denon AVR => Samsung 4k Tv.

Running latest TinkerOS 2.04.

For some reason when connecting through my Denon AVR, there is no output / intermittent output to my TV.
It works just fine when connecting directly to my TV; however i'd rather use my sound system.

It has to do with the numerous threads about how the TinkerOS has issues realizing the correct frequencies/etc for resolutions:

https://www.tinkerboarding.co.uk/forum/thread-633.html
https://tinkerboarding.co.uk/forum/thread-321.html
https://github.com/rockchip-linux/kernel/issues/10

I'd rather just disable 4k within the TinkerOS image itself, and have most/all modes 1080p and lower enabled and supported.

If at the very least I can enable and force 1080p through the boot/console (run level 3 equivalent/no X11) that would be good enough for me.

I've tried the following:
* modifying /boot/config.txt (i'm fairly certain all these options and the file itself is ignored)
* appending video=HDMI-A-1:1920x1200@60 to boot kernel args in /boot/extlinux/extlinux.conf
* recompiling rk3288-miniarm.dtb with 1080p only frequencies as described in this thread: https://tinkerboarding.co.uk/forum/thread-321.html
* Tried using fbset -fb /dev/fb0 -g 1920 1080 1920 1080 32
* anything related to X11 doesn't fit my use case since i'm not running desktop.

None of these options work at all. No matter what I try the boot console/shell *ALWAYS* tries 4k which is broken when connected through my Denon AVR.

This is really frustrating.

Anyone have any idea to force 1080p for boot console/mutli-user target (no X11)?

Either that, or fix the resolution detection problem within the kernel/dtb itself for 2.04?

Many thanks in advance!

I've actually just been trying to disable 4k from the hdmi drivers themselves via:

https://github.com/TinkerBoard/debian_ke...dmi-lcdc.c
https://github.com/TinkerBoard/debian_ke...k-rk3288.c
(and some related c files in the same dir/area)

I have an armbian build env that allows me to build zImage and dtb file just fine. I've been scping them over and putting them in place.

not having much luck as the dclk_v0p keeps ending up with a frequency that is for 4k

Can someone rubber-duck me on whats going on in these files?

I actually fixed 4k through my AVR by merging in some rockchip-kernel into the tinker_debian repo and rebuilding zImage and rk3288-miniarm.dtb and copying to /boot/

would still be nice to know how to force console framebuffer to 1080p because I still can't force it.

Hello nuker311,

I just modified this part in rockchip_drm_vop.c
It can limit the clock, and it will make the resolution not over 1080p@60Hz(clock is about 148.5MHz)
You also can try to modify the maximum clock to see the result.

https://github.com/TinkerBoard/debian_ke..._drm_vop.c

vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
@@@
-if (mode->clock >= 594000 || mode->clock <= 27500)
+if (mode->clock >= 200000 || mode->clock <= 27500)
return MODE_CLOCK_RANGE;

I also provide the kernel image of the above change for you testing
You can download from there.
https://www.asuswebstorage.com/navigate/...8D9899942Y

Yes ashinlin this worked wonderfully! thank you so much!

and for those who had issues with 4k vs their Audio Video Receiver you can try this:

Code:
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi

index d6c45df..0a66921 100755

--- a/arch/arm/boot/dts/rk3288.dtsi

+++ b/arch/arm/boot/dts/rk3288.dtsi

@@ -1016,7 +1016,7 @@

                                   <&cru PCLK_PERI>;

                assigned-clock-rates = <594000000>,

                                       <500000000>, <300000000>,

-                                      <0>, <75000000>,

+                                      <150000000>, <75000000>,

                                       <300000000>, <150000000>,

                                       <75000000>;

        };

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c

index 887040d..ebcf662 100755

--- a/drivers/clk/rockchip/clk-rk3288.c

+++ b/drivers/clk/rockchip/clk-rk3288.c

@@ -96,38 +96,11 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {

        RK3066_PLL_RATE( 312000000, 1, 52, 4),

        RK3066_PLL_RATE( 300000000, 1, 50, 4),

        RK3066_PLL_RATE( 297000000, 2, 198, 8),

-       RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),//2560*1440@60Hz

        RK3066_PLL_RATE( 252000000, 1, 84, 8),

        RK3066_PLL_RATE( 216000000, 1, 72, 8),

-       RK3066_PLL_RATE( 162000000, 1, 81, 12),//1600x1200@60

-       RK3066_PLL_RATE( 154000000, 1, 77, 12),//1920x1200@60

-       RK3066_PLL_RATE( 148500000, 8, 693, 14),//1920*1080@75

-       RK3066_PLL_RATE( 135000000, 4, 315, 14),//1280*1024@75

+       RK3066_PLL_RATE( 148500000, 2, 99, 8),

        RK3066_PLL_RATE( 126000000, 1, 84, 16),

-       RK3066_PLL_RATE( 119000000, 3, 238, 16),//1680*1050@60

-       RK3066_PLL_RATE( 108000000, 1, 72, 16),//1280*1024@60

-       RK3066_PLL_RATE( 88750000, 6, 355, 16),//1440*900@60

-       RK3066_PLL_RATE( 71000000, 3, 142, 16),//1280*800@@60

-       RK3066_PLL_RATE( 74250000, 8, 297, 12),//1280*700@60

-       RK3066_PLL_RATE( 32000000, 1, 16, 12),//1024*600@43

-       RK3066_PLL_RATE( 78750000, 4, 210, 16),//1024*768

-       RK3066_PLL_RATE( 78800000, 15, 788, 16),//1280*720@60

-       RK3066_PLL_RATE( 75000000, 2, 100, 16),//1024*768@70

-       RK3066_PLL_RATE( 65000000, 3, 130, 16),//1024*768@@60

-       RK3066_PLL_RATE( 136750000, 8, 547, 12),//1440*900@75

-       RK3066_PLL_RATE( 106500000, 1, 71, 16),//1280*800@75, 1440*900@60

-       RK3066_PLL_RATE( 88750000, 6, 355, 16), //1440x900

-       RK3066_PLL_RATE( 67500000, 8, 315, 14),//640*480@75

-       RK3066_PLL_RATE( 57280000, 25, 716, 12),//832*624

-       RK3066_PLL_RATE( 50000000, 3, 100, 16),//800*600

-       //RK3066_PLL_RATE( 54000000, 4, 162, 18),//640*480@60

-       RK3066_PLL_RATE( 49500000, 1, 33, 16),//800*600@75

-       RK3066_PLL_RATE( 40000000, 3, 80, 16),//800*600@60

-       RK3066_PLL_RATE( 36000000, 1, 24, 16),//800*600

-       RK3066_PLL_RATE( 35500000, 3, 71, 16),//?

-       RK3066_PLL_RATE( 31500000, 3, 73, 16),//640*480@75

-       RK3066_PLL_RATE( 30240000, 25, 504, 16),//650*480

-       RK3066_PLL_RATE( 28320000, 25, 472, 16),//720*400@70

+       RK3066_PLL_RATE(  48000000, 1, 64, 32),

        { /* sentinel */ },

 };

@@ -239,9 +212,9 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {

        [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),

                     RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),

        [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),

-                    RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),

+                    RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

        [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),

-                    RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),

+                    RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

 };

 static struct clk_div_table div_hclk_cpu_t[] = {

@@ -456,7 +429,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {

                        RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,

                        RK3288_CLKGATE_CON(3), 4, GFLAGS),

-       COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,

+       COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,

                        RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,

                        RK3288_CLKGATE_CON(3), 1, GFLAGS),

        COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c

index 23f1923..eb8386e 100755

--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c

+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c

@@ -1605,7 +1605,7 @@ vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,

        int request_clock = mode->clock;

        int clock;

-       if (mode->clock >= 594000 || mode->clock <= 27500)

+       if (mode->clock >= 200000 || mode->clock <= 27500)

                return MODE_CLOCK_RANGE;

        if (mode->hdisplay > vop_data->max_output.width)

(02-22-2018, 12:53 AM)ashinlin Wrote: [ -> ]Hello nuker311,

I just modified this part in rockchip_drm_vop.c
It can limit the clock, and it will make the resolution not over 1080p@60Hz(clock is about 148.5MHz)
You also can try to modify the maximum clock to see the result.

https://github.com/TinkerBoard/debian_ke..._drm_vop.c

vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
@@@
-if (mode->clock >= 594000 || mode->clock <= 27500)
+if (mode->clock >= 200000 || mode->clock <= 27500)
return MODE_CLOCK_RANGE;

I also provide the kernel image of the above change for you testing
You can download from there.
https://www.asuswebstorage.com/navigate/...8D9899942Y

I tried the kernel and other file you hosted and it worked flawlessly on my HDMI devices (I was stuck at 1024x768 on all of them previously). Unfortunately, I lost wifi in the process.

I will have to keep poking around and see what happened, but thank you so much for fixing the video output issues!

-q

(02-26-2018, 03:10 AM)qfour20 Wrote: [ -> ]
(02-22-2018, 12:53 AM)ashinlin Wrote: [ -> ]Hello nuker311,

I just modified this part in rockchip_drm_vop.c
It can limit the clock, and it will make the resolution not over 1080p@60Hz(clock is about 148.5MHz)
You also can try to modify the maximum clock to see the result.

https://github.com/TinkerBoard/debian_ke..._drm_vop.c

vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
@@@
-if (mode->clock >= 594000 || mode->clock <= 27500)
+if (mode->clock >= 200000 || mode->clock <= 27500)
return MODE_CLOCK_RANGE;

I also provide the kernel image of the above change for you testing
You can download from there.
https://www.asuswebstorage.com/navigate/...8D9899942Y

I tried the kernel and other file you hosted and it worked flawlessly on my HDMI devices (I was stuck at 1024x768 on all of them previously). Unfortunately, I lost wifi in the process.

I will have to keep poking around and see what happened, but thank you so much for fixing the video output issues!

-q

not sure if it's related, but you might have to install the wifi modules with the new/updated kernel image.

https://tinkerboarding.co.uk/wiki/index....e=Software

(02-22-2018, 12:53 AM)ashinlin Wrote: [ -> ]Hello nuker311,

I just modified this part in rockchip_drm_vop.c
It can limit the clock, and it will make the resolution not over 1080p@60Hz(clock is about 148.5MHz)
You also can try to modify the maximum clock to see the result.

https://github.com/TinkerBoard/debian_ke..._drm_vop.c

vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
@@@
-if (mode->clock >= 594000 || mode->clock <= 27500)
+if (mode->clock >= 200000 || mode->clock <= 27500)
return MODE_CLOCK_RANGE;

I also provide the kernel image of the above change for you testing
You can download from there.
https://www.asuswebstorage.com/navigate/...8D9899942Y

Hi ashinlin@, digging a little further I seem to uncover even more bugs with the HEAD (e99e0b471e5887779b61a33c62b41c2ca2674249) of debian_kernel/linux4.4-rk3288.

After finding out that just passing the video= in kernel args here:

label kernel-4.4
kernel /zImage
fdt /rk3288-miniarm.dtb
append console=tty3 rw init=/sbin/init quiet loglevel=3 plymouth.enable=0 disable_splash=1 video=1920x1080@60

I was able to successfully change the boot resolution w/out having to disable 4k altogether.

Some previous posts around the board suggest you need to pass in the target device HDMI-1-A which I found didn't actually work. Just passing in the resolution@refresh works just fine. It %100 changes the boot console framebuffer to desired input resolution@refresh.

However, I found that with the HEAD of debian_kernel, the clk rates here:
https://github.com/TinkerBoard/debian_ke...288.c#L113

Are completely broken. Meaning after I set 1080p resolution for framebuffer using the kernel arg method, my board failed to output display with the HEAD of debian kernel.

It wasn't until I patched zImage and dtb with the patch merge from tinker-kernel (listed in my reply to yours) that 1080p was successfully achieved w/out disabling 4k per your original patch.

I have tested this and deemed it works.

Is it possible to propose a merge fix for debian/linux4.4-rk3288?

Code:
pr0f@ubuntu:~/debian_kernel$ git diff HEAD~1

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi

index d6c45df..0a66921 100755

--- a/arch/arm/boot/dts/rk3288.dtsi

+++ b/arch/arm/boot/dts/rk3288.dtsi

@@ -1016,7 +1016,7 @@

                                  <&cru PCLK_PERI>;

               assigned-clock-rates = <594000000>,

                                      <500000000>, <300000000>,

-                                      <0>, <75000000>,

+                                      <150000000>, <75000000>,

                                      <300000000>, <150000000>,

                                      <75000000>;

       };

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c

index 887040d..ebcf662 100755

--- a/drivers/clk/rockchip/clk-rk3288.c

+++ b/drivers/clk/rockchip/clk-rk3288.c

@@ -96,38 +96,11 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {

       RK3066_PLL_RATE( 312000000, 1, 52, 4),

       RK3066_PLL_RATE( 300000000, 1, 50, 4),

       RK3066_PLL_RATE( 297000000, 2, 198, 8),

-       RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),//2560*1440@60Hz

       RK3066_PLL_RATE( 252000000, 1, 84, 8),

       RK3066_PLL_RATE( 216000000, 1, 72, 8),

-       RK3066_PLL_RATE( 162000000, 1, 81, 12),//1600x1200@60

-       RK3066_PLL_RATE( 154000000, 1, 77, 12),//1920x1200@60

-       RK3066_PLL_RATE( 148500000, 8, 693, 14),//1920*1080@75

-       RK3066_PLL_RATE( 135000000, 4, 315, 14),//1280*1024@75

+       RK3066_PLL_RATE( 148500000, 2, 99, 8),

       RK3066_PLL_RATE( 126000000, 1, 84, 16),

-       RK3066_PLL_RATE( 119000000, 3, 238, 16),//1680*1050@60

-       RK3066_PLL_RATE( 108000000, 1, 72, 16),//1280*1024@60

-       RK3066_PLL_RATE( 88750000, 6, 355, 16),//1440*900@60

-       RK3066_PLL_RATE( 71000000, 3, 142, 16),//1280*800@@60

-       RK3066_PLL_RATE( 74250000, 8, 297, 12),//1280*700@60

-       RK3066_PLL_RATE( 32000000, 1, 16, 12),//1024*600@43

-       RK3066_PLL_RATE( 78750000, 4, 210, 16),//1024*768

-       RK3066_PLL_RATE( 78800000, 15, 788, 16),//1280*720@60

-       RK3066_PLL_RATE( 75000000, 2, 100, 16),//1024*768@70

-       RK3066_PLL_RATE( 65000000, 3, 130, 16),//1024*768@@60

-       RK3066_PLL_RATE( 136750000, 8, 547, 12),//1440*900@75

-       RK3066_PLL_RATE( 106500000, 1, 71, 16),//1280*800@75, 1440*900@60

-       RK3066_PLL_RATE( 88750000, 6, 355, 16), //1440x900

-       RK3066_PLL_RATE( 67500000, 8, 315, 14),//640*480@75

-       RK3066_PLL_RATE( 57280000, 25, 716, 12),//832*624

-       RK3066_PLL_RATE( 50000000, 3, 100, 16),//800*600

-       //RK3066_PLL_RATE( 54000000, 4, 162, 18),//640*480@60

-       RK3066_PLL_RATE( 49500000, 1, 33, 16),//800*600@75

-       RK3066_PLL_RATE( 40000000, 3, 80, 16),//800*600@60

-       RK3066_PLL_RATE( 36000000, 1, 24, 16),//800*600

-       RK3066_PLL_RATE( 35500000, 3, 71, 16),//?

-       RK3066_PLL_RATE( 31500000, 3, 73, 16),//640*480@75

-       RK3066_PLL_RATE( 30240000, 25, 504, 16),//650*480

-       RK3066_PLL_RATE( 28320000, 25, 472, 16),//720*400@70

+       RK3066_PLL_RATE(  48000000, 1, 64, 32),

       { /* sentinel */ },

};

@@ -239,9 +212,9 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {

       [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),

                    RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),

       [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),

-                    RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),

+                    RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

       [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),

-                    RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),

+                    RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

};

static struct clk_div_table div_hclk_cpu_t[] = {

@@ -456,7 +429,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {

                       RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,

                       RK3288_CLKGATE_CON(3), 4, GFLAGS),

-       COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,

+       COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,

                       RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,

                       RK3288_CLKGATE_CON(3), 1, GFLAGS),

       COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,

pr0f@ubuntu:~/debian_kernel$

(02-27-2018, 06:47 AM)nuker311 Wrote: [ -> ]
(02-22-2018, 12:53 AM)ashinlin Wrote: [ -> ]Hello nuker311,

I just modified this part in rockchip_drm_vop.c
It can limit the clock, and it will make the resolution not over 1080p@60Hz(clock is about 148.5MHz)
You also can try to modify the maximum clock to see the result.

https://github.com/TinkerBoard/debian_ke..._drm_vop.c

vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
@@@
-if (mode->clock >= 594000 || mode->clock <= 27500)
+if (mode->clock >= 200000 || mode->clock <= 27500)
return MODE_CLOCK_RANGE;

I also provide the kernel image of the above change for you testing
You can download from there.
https://www.asuswebstorage.com/navigate/...8D9899942Y

Hi ashinlin@, digging a little further I seem to uncover even more bugs with the HEAD (e99e0b471e5887779b61a33c62b41c2ca2674249) of debian_kernel/linux4.4-rk3288.

After finding out that just passing the video= in kernel args here:

label kernel-4.4
kernel /zImage
fdt /rk3288-miniarm.dtb
append console=tty3 rw init=/sbin/init quiet loglevel=3 plymouth.enable=0 disable_splash=1 video=1920x1080@60

I was able to successfully change the boot resolution w/out having to disable 4k altogether.

Some previous posts around the board suggest you need to pass in the target device HDMI-1-A which I found didn't actually work. Just passing in the resolution@refresh works just fine. It %100 changes the boot console framebuffer to desired input resolution@refresh.

However, I found that with the HEAD of debian_kernel, the clk rates here:
https://github.com/TinkerBoard/debian_ke...288.c#L113

Are completely broken. Meaning after I set 1080p resolution for framebuffer using the kernel arg method, my board failed to output display with the HEAD of debian kernel.

It wasn't until I patched zImage and dtb with the patch merge from tinker-kernel (listed in my reply to yours) that 1080p was successfully achieved w/out disabling 4k per your original patch.

I have tested this and deemed it works.

Is it possible to propose a merge fix for debian/linux4.4-rk3288?

Code:
pr0f@ubuntu:~/debian_kernel$ git diff HEAD~1 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d6c45df..0a66921 100755 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1016,7 +1016,7 @@ <&cru PCLK_PERI>; assigned-clock-rates = <594000000>, <500000000>, <300000000>, - <0>, <75000000>, + <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; }; diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 887040d..ebcf662 100755 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -96,38 +96,11 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 312000000, 1, 52, 4), RK3066_PLL_RATE( 300000000, 1, 50, 4), RK3066_PLL_RATE( 297000000, 2, 198, 8), - RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),//2560*1440@60Hz RK3066_PLL_RATE( 252000000, 1, 84, 8), RK3066_PLL_RATE( 216000000, 1, 72, 8), - RK3066_PLL_RATE( 162000000, 1, 81, 12),//1600x1200@60 - RK3066_PLL_RATE( 154000000, 1, 77, 12),//1920x1200@60 - RK3066_PLL_RATE( 148500000, 8, 693, 14),//1920*1080@75 - RK3066_PLL_RATE( 135000000, 4, 315, 14),//1280*1024@75 + RK3066_PLL_RATE( 148500000, 2, 99, 8), RK3066_PLL_RATE( 126000000, 1, 84, 16), - RK3066_PLL_RATE( 119000000, 3, 238, 16),//1680*1050@60 - RK3066_PLL_RATE( 108000000, 1, 72, 16),//1280*1024@60 - RK3066_PLL_RATE( 88750000, 6, 355, 16),//1440*900@60 - RK3066_PLL_RATE( 71000000, 3, 142, 16),//1280*800@@60 - RK3066_PLL_RATE( 74250000, 8, 297, 12),//1280*700@60 - RK3066_PLL_RATE( 32000000, 1, 16, 12),//1024*600@43 - RK3066_PLL_RATE( 78750000, 4, 210, 16),//1024*768 - RK3066_PLL_RATE( 78800000, 15, 788, 16),//1280*720@60 - RK3066_PLL_RATE( 75000000, 2, 100, 16),//1024*768@70 - RK3066_PLL_RATE( 65000000, 3, 130, 16),//1024*768@@60 - RK3066_PLL_RATE( 136750000, 8, 547, 12),//1440*900@75 - RK3066_PLL_RATE( 106500000, 1, 71, 16),//1280*800@75, 1440*900@60 - RK3066_PLL_RATE( 88750000, 6, 355, 16), //1440x900 - RK3066_PLL_RATE( 67500000, 8, 315, 14),//640*480@75 - RK3066_PLL_RATE( 57280000, 25, 716, 12),//832*624 - RK3066_PLL_RATE( 50000000, 3, 100, 16),//800*600 - //RK3066_PLL_RATE( 54000000, 4, 162, 18),//640*480@60 - RK3066_PLL_RATE( 49500000, 1, 33, 16),//800*600@75 - RK3066_PLL_RATE( 40000000, 3, 80, 16),//800*600@60 - RK3066_PLL_RATE( 36000000, 1, 24, 16),//800*600 - RK3066_PLL_RATE( 35500000, 3, 71, 16),//? - RK3066_PLL_RATE( 31500000, 3, 73, 16),//640*480@75 - RK3066_PLL_RATE( 30240000, 25, 504, 16),//650*480 - RK3066_PLL_RATE( 28320000, 25, 472, 16),//720*400@70 + RK3066_PLL_RATE( 48000000, 1, 64, 32), { /* sentinel */ }, }; @@ -239,9 +212,9 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates), [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), - RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates), + RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), - RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), + RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), }; static struct clk_div_table div_hclk_cpu_t[] = { @@ -456,7 +429,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, + COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(3), 1, GFLAGS), COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, pr0f@ubuntu:~/debian_kernel$