Hello.
Rockchip and ASUS are ignoring
(maybe all based on rk3288 as phased-out chip - Rockchip focuses on ROCK64 as currently best supported rk3328 device to spread market adoption 
) or unable to resolve this
issue over 3 month.
I found manual
workaround (for TinkerOS 1.6-1.8 and rockchip-linux ~release-20170417 to ~release-20170705) to get preferred resolution with modify
DeviceTree.
Follow the steps:
- find exact pixel frequency for preferred resolution
- find PLL allowed frequency
- change NPLL ("new pll") fixed frequency in binary DeviceTree ("/boot/rk3288-miniarm.dtb")
Step A: find exact pixel frequency for preferred resolution
option 1 - append "drm.debug=0x4" and reboot:
Code:
# ### append "drm.debug=0x4" to linux startup to get following
# cat /boot/extlinux/extlinux.conf
label kernel-4.4
kernel /zImage
fdt /rk3288-miniarm.dtb
append earlyprintk console=ttyS1,115200n8 console=tty1 root=/dev/mmcblk0p2 rw init=/sbin/init drm.debug=0x4
# reboot
# dmesg | awk '/drm:drm_mode_debug_printmodeline/ {print $5, $7}' | sort -u
100:"640x480" 25175
...
102:"1280x1024" 135000
...
96:"1280x1024" 108000
...
99:"640x480" 31500
.
option 2 - decode EDID:
Code:
# od -t x1 -An /sys/devices/platform/display-subsystem/drm/card0/card0-HDMI-A-1/edid
00 ff ff ff ff ff ff 00 22 f0 93 26 01 01 01 01
34 13 01 03 80 26 1e 78 ee ee 95 a3 54 4c 99 26
0f 50 54 ad ef 80 81 80 01 01 01 01 01 01 01 01
01 01 01 01 01 01 30 2a 00 98 51 00 2a 40 30 70
13 00 7c 2c 11 00 00 1e 00 00 00 fd 00 30 4c 18
53 0e 00 0a 20 20 20 20 20 20 00 00 00 fc 00 48
50 20 4c 50 31 39 36 35 0a 20 20 20 00 00 00 ff
00 43 4e 34 39 35 32 30 32 59 43 0a 20 20 00 31
Decode EDID
online and check with
VESA DMT or CEA standards timing. From VESA DMT standard and "EDID Timing Bitmap" or "EDID Detailed Timing Descriptor" - "1280 x 1024 @ 60 Hz" -> 108000 kHZ.
Step B: find PLL allowed frequency
The NPLL ("new pll") can be programmed to fixed frequency by
rk3288_pll_rates. Oneliner bash script helps find PLL frequency that is multiple of requested pixel frequency.
Code:
# echo -n "Enter pixel freqency (in kHz): "; read freq; let freq=freq*1000; echo "Compatible PLL frequnces"; for pll in 2208000000 2184000000 2160000000 2136000000 2112000000 2088000000 2064000000 2040000000 2016000000 1992000000 1968000000 1944000000 1920000000 1896000000 1872000000 1848000000 1824000000 1800000000 1776000000 1752000000 1728000000 1704000000 1680000000 1656000000 1632000000 1608000000 1560000000 1512000000 1488000000 1464000000 1440000000 1416000000 1392000000 1368000000 1344000000 1320000000 1296000000 1272000000 1248000000 1224000000 1200000000 1188000000 1176000000 1128000000 1104000000 1008000000 912000000 891000000 888000000 816000000 798000000 792000000 768000000 742500000 696000000 600000000 594000000 552000000 504000000 500000000 456000000 408000000 400000000 384000000 360000000 312000000 300000000 297000000 252000000 216000000 148500000 126000000 48000000; do let rest=pll%freq; if ((rest == 0)); then printf "0x%x (%d)\n" $pll $pll; fi; done
Enter pixel freqency (in kHz): 108000
Compatible PLL frequnces
0x80befc00 (2160000000)
0x73df1600 (1944000000)
0x66ff3000 (1728000000)
0x5a1f4a00 (1512000000)
0x4d3f6400 (1296000000)
0x46cf7100 (1188000000)
0xcdfe600 (216000000)
Now choose (probably lowest one) frequency for
NPLL = 0xcdfe600 (216000000).
Step C: change NPLL ("new pll") fixed frequency in binary DeviceTree ("/boot/rk3288-miniarm.dtb")
option 1 - update source DTS and recompile kernel
- open source arch/arm/boot/dts/rk3288.dtsi
- find
clock-controller (cru) for rockchip-linux (or for
TinkerOS variant of kernel) and replace NPLL in assigned-clock-rates from 500000000 to 216000000 (on 2nd or 5th position kernel depended).
- recompile kernel (see other post) and copy arch/arm/boot/dts/rk3288-miniarm.dtb to /boot on bootable MMC and reboot
option 2 - decompile DTB, update, compile DTS
Code:
# apt-get install device-tree-compiler
# cd /boot
# dtc -i dtb rk3288-miniarm.dtb > orig.dts
# cp orig.dts new.dts
# vi new.dts
# ### find "assigned-clock-rates" for "clock-controller" 0x1dcd6500 -> 0xcdfe600
# ### 2nd position in rockchip-linux/kernel, 5th position in tinkeros_debian_kernel release 1.8
# ### check with diff
# diff -u orig.dts new.dts
--- orig.dts 2017-07-10 16:08:17.000000000 +0000
+++ new.dts 2017-07-10 13:50:31.000000000 +0000
@@ -1120,7 +1120,7 @@
#clock-cells = <0x1>;
#reset-cells = <0x1>;
assigned-clocks = <0x7 0x4 0x7 0x5 0x7 0xd1 0x7 0x1dd 0x7 0x16a 0x7 0xd2 0x7 0x1de 0x7 0x16b>;
- assigned-clock-rates = <0x2367b880 0x1dcd6500 0x11e1a300 0x8f0d180 0x47868c0 0x11e1a300 0x8f0d180 0x47868c0>;
+ assigned-clock-rates = <0x2367b880 0xcdfe600 0x11e1a300 0x8f0d180 0x47868c0 0x11e1a300 0x8f0d180 0x47868c0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
# dtc -i dts new.dts > rk3288-miniarm.dtb
# reboot
You can check "PLL" and "CLK" assignments in kernel runtime with "
less /sys/kernel/debug/clk/clk_summary". Search for "pll_npll" and "dclk_vop0".
Now the resolution for boot console and X is set to requested 1280x1024 @ 60. There is no need to add additional data to command line linux options or to xorg.conf or run xrandr or fbset because EDID mode is validated and accepted by kernel DRM/FB.
There is also side effect "sclk_gpu" clock (mali) cannot use this "NPLL" as source (
request for 100/200/300/400/600 MHZ) - it uses "GPLL" now (eg. 99/198/.../594 MHZ).
Happy hacking !
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